How To Build Register File

Lab iii - Register File
Learning Outcomes
Preliminary
Exercises
- Do 1 - Annals File
- Do 2 - Registerfile Testbench
- Practise iii - Regfile Top Circuit
  - Controlling the Datapath Circuit
- Exercise 4 - Implementation and Download
Pass Off

Lab 3 - Annals File

The register file is an another important component of any processor system. The annals file stores the values of the registers used by the processor. Almost all instructions read from and/or write to the register file. You will create a register file in this laboratory that you volition include in your RISC-Processor used in a later on lab.

Avg Hours: half-dozen.one (Winter 2021)

Learning Outcomes

Understand how multi-ported memoriess operate
Be able to create multi-ported memories in SystemVerilog
Create a synchronous multi-ported register file

Preliminary

All processors include internal registers that are used for performing fast operations in conjunction with the ALU. The register file for the RISC-V processor contains 32x32-bit integer processor registers. The annals file you will create in this lab will exist reused in time to come labs and function of your final RISC-V processor.

A number of instructions in the RISC-5 instruciton fix involve reading two values from the register file and writing the result into the register file (i.due east., the register instructions). To maximize the speed of executing these instructions it is necessary to read ii registers from the register file and write one register into the register file at the same time. A memory that supports the ability to perform more than one read or write during a clock cycle is known as a 'multi-ported' retention. The register file you will create volition be designed to support the simultaneous reading of two registers and the writing of one register.

The FPGA nosotros are using for the lab includes a dedicated logic element named a "Distributed RAM" that provides the building cake for a multi-ported distributed memory. In social club to use these memory elements y'all need to write your SystemVerilog in a very specific manner. If written properly, the synthesis tool volition "infer" these special purpose multi-ported memories from your SystemVerilog code. This preliminary will depict how to write your SystemVerilog in a manner that infers these elements. This example is based on the examples provided in the Xilinx Synthesis Guide (meet page 118).

The kickoff step necessary for inferring the multi-ported memory is to declare a multi-dimenssional array logic array. The following example demonsrate how to declare a memory array that has eight words and 8-bits broad for each word:

            // Declare multi-dimensional logic array (8 words, 8 bits each) logic [7:0] register[7:0];

The beginning array index afterward logic indicates that there are 8 $.25 in each word. The second array index after register indicates that at that place are eight words.

The next step in describing the register file retentiveness is to initialize the memory to all zeros. The multi-dimensional array is initialized using a SystemVerilog 'initial' cake as follows:

            // Initialize the viii words integer i; initial   for (i=0;i<8;i=i+1)     annals[i] = 0;

The final step is to describe the behavior of the memory in an e'er block. The code example beneath demonstrates how to properly describe the memory using a "write-first" way (i.due east., when you write to the aforementioned address that you read from, return the new write value rather than the sometime value). A detailed description of this code will exist given below the code example (notation the use of the not-blocking <= operator).

                          one: always_ff@(posedge clk) begin  2:   read1 <= register[addr1];  3:   read2 <= register[addr2];  iv:   if (write) begin  five:     register[writeAddr] <= writeData;  6:     if (addr1 == writeAddr)  seven:         read1 <= writeData;  viii:     if (addr2 == writeAddr)  ix:         read2 <= writeData; 10:   end 11: end

An always_ff block is used in line 1 with the global clock. This suggests that this memory is synchronous significant that information technology operates synchronously with the global clock. All reads and writes volition occur at positive clock edges rather than with some other asynchronous control bespeak. Lines 2&3 demonstrate how to access elements of the ii dimentional array. Ii accesses are performed simulataneously on the two-dimentional register signal: i is indexed with the point addr1 and the other with the signal addr2. Because there are eight elements of the array, both addr1 and addr2 should exist 3 bits in size (thus allowing these signals to select any of the viii words in the array). The consequence of these accessess are assigned to the signals read1 and read2. These signals should be 8 bits as each word in the array is 8-$.25 broad.

Lines 4-nine define the write behavior of the memory. If the single-bit write control signal as '1', and so the 8-bit bespeak writeData will be written to the element of the register assortment specified past the iii-bit signal writeAddr (see line 5). Lines 6-nine handle the example when one or both of the read ports are reading from the same address that is beingness written to. If this is the cases, then the respective read value is updated with the new writeData rather than the onetime value that was read in lines two-3.

Answer the questions in learning suite regarding the behavior of this retention.

The waveform beneath demonstrates the operation of this multi-ported memory. All memory locations this memory have been initialized to zero. During clock cycle 0, 'addr1' and 'addr2' both accept the value 0 indicating that the value of address 0 volition be read from both ports. The outcome of these reads show upwardly during clock cycle ane (a value of '00' is read from both ports since all locations are initialized to zero). The 'write' betoken is low during this clock cycle and so no writes occur on the positive clock edge at the stop of clock wheel 0.

In clock cycle 1, the 'write' signal is asserted to signal that the value 'a5' (on 'writeData') will occur to address '3' ('writeAddress'). This write volition occur on the rising edge of the clock at the end of clock cycle 1. The value of the retention at address 1 is read from Port 1 and the value of the memory at address 2 is reaad from Port 2. Both of these values are 0 and appear during the adjacent clock bicycle.

Demonstrate your understanding of the performance of the multi-port memory by completing the waveform above in the learning suite exam.

Exercises

Practise 1 - Annals File

In this practice y'all will create a annals file module that you volition utilise within another top-level module in this lab and for your RISC-V processor in after labs of the course. Begin this exercise by creating a new SystemVerilog file named regfile.sv (within the lab03 directory of your repo) and add together the following ports to this module:

Module Name: regfile
Port Name	Management	Width	Purpose
clk	Input	i	Global clock
readReg1	Input	five	Address for read port i
readReg2	Input	5	Address for read port 2
writeReg	Input	v	Address for write port
writeData	Input	32	Information to be written during a write
write	Input	1	Control point indicating a write
readData1	Output	32	Data read from port 1
readData2	Output	32	Data read from port 2

After creating the empty module, implement a 32x32-fleck register file based on the lawmaking examples given in the preliminary. The primary departure between the preliminary instance and the annals file you should create is that the preliminary case only independent 8 words in the register file and the words were 8-bits.

You will demand to submit the file 'regfile.sv' inside of your repository.

How many total bits are there in this register file?

Important: At that place is one other change that y'all must make in your register file to use it within the RISC-V processor. You demand to add logic that will make certain that address 0 is never written to (i.e., register x0). Register 0 (x0) is always the constant 0 and whatever writes to this register that modify the value will cause problems when executing RISC-5 code. To forbid address 0 from being written, add additional logic that only allows a write to the register file to occur when (1) the write betoken is asserted and (ii) writeReg!=0.

After creating your register file, create a tcl simulation file named regfile_sim.tcl and simulate the writing of at least two registers and the reading of at least three locations (making sure yous read dorsum one of the registers you wrote to). Likewise, verify that writing a non-zero value to register 0 will not alter the constant zero value that should be in this regitster.

Y'all will need to submit your simulation regfile_sim.tcl file as part of your "Pass Off" below.

Exercise 2 - Registerfile Testbench

The simulator and waveform viewer are very important tools that you will use throughout the semester. The amend y'all know how to use these tools the more than effective and efficient you will be in completing the labs in this class. When simulating with a testbench, only the top testbench signals show upwards in the simulator. Yous will be interested in looking at the signals in your circuit to make sure your circuit is working correctly. Review the Simulation Tutorials to learn how to add together your module signals in the simulator and other simulation tips and techniques.

Respond the questions in the lab report regarding the simulation tools.

Because your register file volition be used within several processors in later on labs, it is essential that the annals file is fully tested. For this exercise you will simulate your register file with the tb_regfile.sv testbench provided in the starter code. This testbench will simulate a large number of cases to make sure it is working properly for this laab and future labs.

Create a new simulation set named sim_2 and add together the tb_regfile.sv testbench to this simulation ready as desribed in the previous lab. Simulate and debug your circuit until you go a successful simulation. An example of a successful simulation is shown beneath:

            *** Start of Regfile Testbench Simulation *** relaunch_sim: Time (south): cpu = 00:00:00 ; elapsed = 00:00:18 . Retentivity (MB): peak = 1095.965 ; gain = 0.000 run all *** Testing x0 register at time 140 ns *** Testing write to each register at 830 ns *** Testing simultaneous reads and writes to each register at 1500 ns *** Testing different read addresses at 1860 ns *** Testing random transaactions at 2180 ns *** Successful simulation. Ended at 5670 ns ***

Answer questions about the testbench results in learning suite.

Practice iii - Regfile Top Circuit

For this practise, you lot will create a superlative-level excursion that uses both your register module and the alu module you created in the previous lab.
The pinnacle-level circuit you volition create is a elementary dataflow excursion that is similar to the RISC-Five datapath circuit yous volition create in lab 5. This circuit will allow you to store values in the register file and perform ALU operations on the values stored in the ALU much similar the RISC-V processor. The difference is that you will need to control the functioning of the ALU and register file with buttons and switches manually to simulate the operaetion of the processor controller. The post-obit word will describe the excursion and then describe how to control the circuit.

Brainstorm by creating a new file named regfile_top.sv with the module named regfile_top and add the following tiptop-level ports:

Module Proper name: regfile_top
Port Name	Management	Width	Purpose
clk	Input	1	Global clock
btnc	Input	1	Centre Button
btnl	Input	1	Left Push
btnu	Input	1	Upwards Button
btnd	Input	1	Down Push
sw	Input	16	Switches for data input)
led	Output	16	LEDs for accumulator output

This circuit will combine the ALU you lot created in the previous lab with the register file you created in the previous exercise. This excursion will allow you to perform bones ALU and annals operations by setting the switches and buttons and looking at the results on the LEDs. You lot volition be able to load whatsoever value into any register in the register file and yous will be able to perform any of the ALU operations on the data in the annals file and store the results back into the register file. The diagram below describes the compages of this excursion.

Address Register

Begin by creating a 15-bit register that controls the three ports of the register file. This annals should be reset by the global reset point ('btnu') and loaded with the bottom 15 switches (sw[14:0]) when 'btnl' is pressed. The 15 bits of the address register will exist used to control the address of the three ports of the annals file as follows:

$.25[4:0] - the annals accost for the first operand (readReg1 port)
bits[ix:5] - the register address for the second operand (readReg2 port)
bits[14:10] - the register address for the desitnation annals (writeReg)

Register File

Next, instance your register file and hook upward the address ports of the register file to the accost register every bit described in a higher place. The regWrite betoken used to write a new value into the register file should be set when 'btnc' is pressed. Yous will need to create a synchronizer and ane-shot circuit to prevent this signal from being asserted more than once when the push is pressed. The signals going to the other ports of the register file will be described beneath.

ALU

Add your ALU to your annals equally shown in the diagram above. Specifically, attach the output of the readData1 signal on the annals file to the op1 input of the alu and attach the output of the readData2 point on the register file to the op2 input of the alu. All opereations performed by the ALU will exist betwixt the values establish in the register file. The 'alu_op' input of the ALU should exist driven by switches [iii:0].

Write Data The input to the writeData signal is driven by a multiplexer that chooses between the ii types of operations. When sw[15]=0, this multiplexer will laissez passer the ALU issue to the writeData (i.e., the output of the ALU will be written into the annals file). When sw[fifteen]=one, the multiplexer will pass a 32-bit sign-extended value of the lower fifteen switches. Begin by creating a 32-fleck sign-extended value of the lower xv switches. Next, create a multiplexer that chooses betwixt the output of the ALU and the 32-bit sign extended value. Adhere the output of this multiplexer to the writeData input of your register file.

LED Outputs The last pace in creating the excursion is to attach the LEDs. Create a multiplexer that selects the lower xvi-bits of the readReg1 when 'btnd' is NOT pressed and selects the upper 16-$.25 of the readReg1 point when 'btnd' IS pressed. This will allow the user to examine the full 32-bit value of readReg1. A one shot is not needed for 'btnd'.

Controlling the Datapath Circuit

If yous have created your circuit, you will need to test it with a TCL file to demonstrate the pinnacle-level register file. The notes below describe how a user (and your TCL file) volition perform operations on this circuit.

Pace 1: Set Accost Annals

The outset stride in performing an performance is to set the 'Address Register'. The address annals holds three different addresses: an address for the first source operand, an address for the second source operand, and address for the result destination. To set the value of the address regsiter, the user volition ready the switches as follows:

sw[4:0] - the annals address for the first operand (readReg1 port)
sw[9:5] - the register address for the second operand (readReg2 port)
sw[14:ten] - the register address for the desitnation register (writeData)

For example, if a user wanted to perform an operation between register x1 and x3 and store the event in x5, the user would prepare switches [four:0] to '00001' to indicate register x1 for operand ane, switches [ix:5] to '00011' to indicate annals x3 for operand 3, and switches [14:ten] to '00101' to signal that the result should be stored in register x5. Concatenating these signals together, the user would set the switches to '001010001100001' (note that switch xv will be set in the next pace).

After setting the switches to betoken the source operand addresses and the destination accost, the user would press 'btnl' to load the address register with this value.

Footstep 2: Set Performance Command

The second step in performing an operation is to bespeak what blazon of performance to perform with the regsiter data. At that place are 2 types of operations: conventional ALU operations and a load value operation with the switches. The ALU performance type is determined by switch 15. If switch 15 equals 0 (sw[xv]=0) and so a conventional ALU opereration will be performed, if switch xv equals 1 (sw[15]=one), and then a new value indicated by the switches is loaded into the annals file. Each of these operation types are described beneath.

ALU Operation

To perform an ALU operration, sw[15] should exist set to aught. Side by side, the ALU performance that is to exist performed should be set on switches[iii:0]. The constants for the ALU functioning were defined in the previous lab. For example, if the user wants to perform an 'addition' between 2 operations, sw[3:0] should be set to '0010' to indicate an addition performance. Any of the ALU operations supported past your ALU can be executed.

New Value Load Operation

To load a new value into a annals, sw[fifteen] should exist set to on (sw[15]=i). The other xv switches should be set to the signed value to be loaded into the destination register. This 15-scrap number volition exist sign extended to 32-bits and loaded into the destination as specified in the address register. For example, if the number 693 is to be loaded into a annals, the switches [14:0] are set to "000001010110101" and sw[xv]='1'.

Step 3: Perform Performance

Subsequently the address register has been set and the performance specified, the operation is performed when the user presses 'btnc'.

Instance Performance

The following case demonstrates how to perform the functioning x4=43+27. The post-obit iii operations must be executed on the system to complete this functioning:

            ane:x1 = 43 ii:x2 = 27 iii:x3 = x1 + x2

Each functioning is composed of two phases: the load address phase and the operation phase. The following table demonstrates what buttons and switches must exist set up to complete this operation:

Step	Switches	Buttons	Notation
1a	0 00001 00000 00000 (0x0400)	btnl	Load ane into write accost (0 in others)
1b	1 000 0000 0010 1011 (0x802b)	btnc	Load constant 43 into register one
2a	0 00010 00000 00000 (0x0800)	btnl	Load 2 into write address (0 in others)
2b	one 000 0000 0001 1011 (0x801b)	btnc	Load constant 27 into register two
3a	0 00011 00010 00001 (0x0c41)	btnl	Load iii into write address, one in A port address, 2 in B port address
3b	0 00000000000 0010 (0x0002)	btnc	Perform Improver Functioning

Demonstrate your agreement on how to control this datapath by determining the values of the buttons and switches necessary to complete the operation listed below:

            i:x7 = -35 2:x9 = x0 ^ x7 three:x15 = x7 & x9

Step	Switches	Button
1a
1b
2a
2b
3a
3b

Complete the tabular array on learning suite.

After creating your summit-level excursion, simulate your circuit with a tcl script named regfile_top_sim.tcl. This tcl script should simulate your circuit as follows:

Write the value 0x00001234 to register 1
Write the value 0x00003678 to register 2
Perform an add operation betwixt register 1 and register 2 and store the result in register 3

You volition need to submit your simulation regfile_top_sim.tcl file as office of your "Pass Off" below.

In improver to your .tcl simulation, you will need to simulate your top-level register file with a top-level testbench. Create a new simulation set up that includes the tb_regfile_top.sv testbench from your starter code. This testbench volition simulate button presses and switches to check to see that your top-level register file circuit is working properly. This testbench will print a number of letters during the execution of your excursion and provide a message indicating that it has passed the testbench.

Exercise iv - Implementation and Download

In this final exercise, you will go through the steps required to synthesize, implement, and generate a bitstream for your peak-level register module.

To proceed with the implementation of your calculator circuit create a new '.xdc' constraints file named regfile_top.xdc to map the top-level I/O of your circuit to actual pins on the Basys3 board. When you accept completed this file, add this equally a constraint file to your Vivado project. Later on creating this file and adding it to your projection, you tin proceed with the synthesis, implementation, and bitstream generation steps of this procedure.

Indicate the number of resources consumed by this design and the WNS in the laboratory report.

Note: If your register file circuit was synthesized properrly, it should allocate some "LUTRAM" elements. If you do not have LUTRAM primitives in your suynthesized blueprint then in that location is a trouble and you should work with a TA or instructor to resolve it earlier proceeding.

Download

Once you lot have successfully generated a bitstream for your calculator circuit, download this bitstream to your Basys3 board. Experiment with your excursion and verify that information technology functions as expected.

Pass Off

To create your submission, make sure the following files are committed in your 'lab03' directory:

regfile.sv
regfile_sim.tcl
regfile_top.sv
regfile_top.xdc
regfile_top_sim.tcl

Make sure you do not add unnecessary files (including Vivado project files) to your repository. Tag your repository with the string lab3_submission and push your repository back to the origin. Exam your submission by running the lab03_passoff.py pass-off script found in the starter code. Review the instructions for submitting and passing off labs to brand sure you accept completed the lab properly.

Include the post-obit information at the end of your laboratory report.

How many hours did y'all work on the lab?

Provide any suggestions for improving this lab in the future.